TSMC has developed an improved magnetoresistive memory that consumes 100 times less energy

TSMC has developed an improved magnetoresistive memory that consumes 100 times less energy

TSMC, together with scientists from the Taiwan Industrial Technology Research Institute (ITRI), demonstrated a jointly developed SOT MRAM memory. According to TechNewsSpace, the new drive is designed for in-memory computing and use as a high-level cache memory.

The new memory is faster than DRAM and retains data even after the power is turned off. It is designed to replace STT-MRAM memory and consumes 100 times less energy during operation.

Experimental plate with SOT-MRAM chips. Image credit: TSMC/ITRI

Among other promising non-volatile memory options, spin-transfer magnetoresistive memory (STT-MRAM) has long been a contender for high-level (L3 and higher) cache memory and for in-memory non-volatile computing among other storage options .

In this memory variant, the magnetization is transferred to the memory cell through a tunnel junction using a spin-polarized current. For this reason, the energy consumption of STT-MRAM was several times lower than that of conventional MRAM memory, in which recording was carried out using an induced electromagnetic field.

SOT MRAM memory has gone even further. Recording (magnetization) of the cell (ferromagnetic layer) occurs with the help of spin-orbit moment. The effect occurs in the conductor at the base of the cell due to a combination of two phenomena: the spin Hall effect and the Rashb gem effect.

As a result, the ferromagnet adjacent to the conductor is under the influence of the magnetic field induced by the spin current in the conductor. This results in SOT-MRAM requiring less power to operate, although the real breakthrough is yet to come.

Write and read current paths for two types of MRAM cells. Image source: National University of Singapore

Other advantages of SOT-MRAM are separate recording and reading circuits, which positively affects performance, as well as increased wear resistance.

“This unit cell simultaneously provides low power consumption and high-speed operation, reaching speeds of up to 10 ns. The overall computing performance can be further improved by implementing in-memory computing circuits. In the future, this technology has the potential for applications in high-performance computing (HPC), artificial intelligence (AI), automotive chips, etc.” said Dr. Shi-Chi Chang, Director General of ITRI’s Electronics and Optoelectronics Research Laboratories.

SOT MRAM with latencies down to 10 ns is closer to SRAM (latencies down to 2 ns) than traditional DRAM with latencies up to 100 ns and above. And of course, with delays from 50 to 100 μs, it is significantly faster than the popular 3D NAND TLC today.

But SOT-MRAM memory will not appear in processors and controllers either tomorrow or the day after tomorrow, just like STT-MRAM memory, which has been in development for more than 20 years. All this is not very obvious, although it is generally necessary for efficient in-memory computing and self-powered devices.

Earlier, ProIT reported that in In 2024, Intel plans mass production of the 15th generation Arrow Lake with a 2nm (20A) chip.

We previously reported that TSMC’s 3nm chips will be exclusive to Apple this year, as Intel is behind schedule.

Read also on our website: ASML and Samsung invest $761 million in the development of new generation chips in South Korea.

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