Those who expect scientific content from reading – I ask you not to read immediately, there is nothing here that you can refer to except your own works, which means that the publication does not contain scientific content – please forgive me in advance for such audacity, and note that my warning is still about it was.

In fact, considering the last post (the consequences of which I will try to correct, since probably many have decided that this is a figment of the imagination – a new architecture) – of the preprocessor, as I consider the processor and the post processor. In order to understand the train of thought better, and that all this is not fantasy, but the result of work – it is worth reading this previous publication, it is not very long – but it will take time, although it is not very difficult.

Having familiarized yourself with it, it will be clear what is meant by code modifications (changing formulas and disabling lines of code in runtime), code modifications simply include and disable executable commands and code. At first, I assumed that the cache of bridges would consist of parallel parts, and most likely, in such a pipeline architecture, it would have to ensure the operation of labels and pointers (but not about them now). In some publications I was commented that there were not enough graphics and drawings (like about polarization for machine vision), but as you can see from the publication linked above – it turned out that one block diagram was enough to polish and modify the entire code, and even to the extent that to think about new architecture.

The architecture of the preprocessor (it’s something like a GPU core) and what it requires.

How do I need new types of data for the operation of such a pipeline, namely to separate cycles into a separate type and create a cache for them. The urgent need for this can be seen from the publication in the link above, who does not like to read – please do not scold me, because I am not writing about the fruits of imagination, but about the results of work and conclusions. The idea of ​​creating a cache of bridges came when analyzing the same code and when there was an obvious need to modify the code in runtime. Then there should be a cache of commands, followed by a cache of variables before the ALU. The code executed on the preprocessor must be compiled under it, and when loaded into the preprocessor, be distributed among three caches: commands, bridges, and cycles. All this was already available for review by me and the scheme was in the last publication about the architecture of the computing machine. And further, as I promised – the formulas were analyzed (I had to remember, because I wrote them in a hurry and did not make any notes), I did not find anything interesting in them, and everything works in this form: I commented on the initial formula

 //           TracerX := x - ( znak*sign(trunc((1+sign(y-trunc(y/(stepsBig+1))*(stepsBig+1)-steps)/2))) +  formula1)+1;
              TracerX := x - formula1+1;
              if (y mod SummSteps)-steps = 0 then TracerX:= TracerX-znak;
              if (y mod SummSteps)-steps > 0 then TracerX:= TracerX-znak;

But there is nothing particularly interesting there. Now to the most interesting thing – a processor without a command counter. This idea came to me immediately, as soon as I returned from the formulas to the pipeline scheme. I will present a slightly modified scheme, since it already has elements for the description of the pipeline without a command counter.

That is, the schematic image shows the conveyor (core) of the preprocessor from the second block and above. According to the previous publication, the role of the CPU analog will be performed by the postprocessor. Both the preprocessor and the postprocessor are physical processors in this architecture (in IT, the preprocessor is a software product).

What is shown here is the order of cache cycles – it is not worth dwelling on it, it is just worth noting that the cycles here are separated into some type and have their own cache. This is done not just like that, but so that the control means, while the command is being executed in the following caches from right to left, if possible, execute their command over the cache of the cycle and transfer it to the waiting mode for the completion of work with the following caches, conditionally the principle – “touch and go on”, or something like the operation of some multi-link automaton. The cache of bridges is the most interesting part, in my opinion, because it opens up the possibility of implementing a processor without a command counter, however, I initially had high hopes for this cache and type, because with its help it was planned to carry out small modifications of the code at runtime, but ideas it was not as beautiful as it is now. Part of the bridge cache is attached to the instruction cache in the diagram – green cells, bits containing either zeros or ones. The same size cell on the right – code execution bits. In the diagram, the red cell with a unit represents the address of the command cache from which the command is read. Further, the text description becomes more complicated, how it should work after reading the command, the command cache must go to the next address, for this, a signal is sent along the bridge bit line, and if the bridge bit contains a unit in the next address, then it (probably by means of the mesfet type, here I complete noob and I have a lot to learn) hardware blocks the signal from passing further down the bridge bit line, if zero – then freely passes without activating its current address for reading (not writing a one to it), as soon as the bridges bit with one is reached – in its execution bit will be overwritten to one, and it will initially be set to zero. Of course, in electronics, unlike algorithms and methods, I am a novice, and there will be no quick results and publications from me. The implementation, as a beginner, seems not difficult to me – two tracks with minimal mesfet-type means (this is not accurate, since I am a complete noob here, but not completely), of course, I do not know how easy it is to implement it on an FPGA, well, of course, two bit cells on each instruction cache address: execution bit and bridge bit. Modifications of the program are planned to be performed using commands to set the state of the bridge bits. I’m sorry for my lame terminology here – I promise to bring everything up to the next, not fast, publication, with already some results. Initially, from the idea of ​​”polarization of machine vision”, I solved the task of finding the fastest methods, algorithms, this was also preserved when writing a map generator (as part of the project), I expect the same effect from this architecture – there will be no need to look for an address in the cache commands, the transition to the next one will be done by hardware and fully automatically. If desired, the core can be made multi-mode, or if necessary, this experience of the bridge cache (without the command counter) can be applied to other caches of the processor. All caches are supposed to be available to the programmer for manipulation with commands.

If someone has a desire to help me learn new knowledge to continue my work, I will provide information: OS Ubuntu 22.04, from useful programs – Qucs Spice, I am just about to start learning it in a short prime time between the time that goes to the main work and sleep, minus some ordinary household everyday relations. There was just a person who seemed not to be interested, this information is more for him, well, plus a virtual box, but it may not be necessary at all. As part of the project, I will not refuse any help. I don’t know about you, but I haven’t lost hope for decades (the very solution to the problem of machine vision was marked by me as my way to create AI, well, the truth is that I came to architecture, after algorithms). Please don’t scold me – I don’t touch anything that belongs to others, all my efforts and works are purely my own, that’s why I continue to follow my own path. If someone thinks that this is an intrusion on my part into his field, it is his mistake, because the field is not his, but the result of the work of generations and minds, and patents for inventive activity have not yet been invented, and it is unlikely that this will happen. . And by the way, I will repeat just in case (many people do not read carefully) – all this is a continuation of the work: stage, analysis, continuation; stage, analysis, continuation… – no fantasies. The beginning of the electronic scheme has already been laid by me (it is precisely according to the cache of commands and bridges), but I am somewhat shy to publish it, because I am a noob.

Thank you for your attention, with the hope of understanding.